A typical SRAM device is designed to store many thousands of bits of information. These bits are stored in individual cells, organized in an array of rows and columns to make efficient use of space on a semiconductor substrate containing the SRAM device. A commonly used cell architecture is known as the “6T” cell, by virtue of having six MOS transistors. Four transistors defining an SRAM cell core or memory element are configured as cross-coupled CMOS inverters, which act as a bistable circuit that can indefinitely hold a memory state imposed on it while powered. Each CMOS inverter includes a load or “pull-up” transistor and a driver or “pull-down” transistor. The outputs of the two inverters will be in opposite states, except during transitions from one state to another.
Two additional transistors are known as pass gate transistors, which provide access to the cross-coupled inverters during a read operation or a write operation. The gate inputs of the pass gate transistors are typically commonly connected to a word line for row access. The pass gate transistors are used to respectively connect each side of the memory element to a “true” bit line BLT and its complement (or “bar”) bit line BLB for column access. In SRAMs having interleaved words in a row, half-selected cells (non-selected columns in a selected row) are subject to upset when fully selected cells are being written. This can limit the assist given to writing into the cell (e.g., using a boosted word line signal for write).
Some SRAM cell architectures, such as an 8T SRAM cell architecture, include a read buffer that isolates the storage element during a read operation. Nevertheless, half-selected cells in a write cycle are subject to upset. Read and write-back is one approach that can be used to preserve the state of half-selected cells in a write cycle. However, using read and write-back often comes at the expense of considerable dynamic power. Improvements in this area would prove beneficial in the art.